In recent years, use of an instruction set simulator (ISS) enables software debugging before production of actual hardware. The ISS is a simulator to convert an instruction set of a target central processing unit (CPU) to an instruction set of a host CPU and execute the instruction set after the conversion. The target CPU is a processor of a target machine to be simulated. The host CPU is a processor of a host machine to execute the simulation.
Conventionally, there is a method of simulating simultaneous operations of a plurality of systems including respective processor cores having different operating frequencies (see, for example, Patent Literature 1). As in this method, simulation of a multi-core CPU system and simulation of a multi-CPU system are also enabled. The multi-core CPU system is a system in which a plurality of cores are mounted in a single processor. The multi-CPU system is a system having a plurality of processors.